RESEARCH ON THE PACKING ALGORITHM FOR ANTI-SEU OF FPGA BASED ON TRIPLE MODULAR REDUNDANCY AND THE NUMBERS OF FAN-OUTS OF THE NET

作     者：Cui Xiuhai Yang Haigang Peng Yu Peng Xiyuan 

作者机构：Automatic Test and Control InstituteHarbin Institute of Technology Institute of ElectronicsChinese Academy of Sciences 

出 版 物：《Journal of Electronics(China)》 (电子科学学刊（英文版）)

年 卷 期：2014年第31卷第4期

页      面：284-289页

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：Supported by the National Natural Science Foundation of China(No.61106033) 

主　　题：Field Programmable Gate Array (FPGA) Triple Modular Redundancy (TMR) Packing algorithm Fan-outs of the net Critical path delayCLC number:TN473 

摘      要：Static Random Access Memory(SRAM) based Field Programmable Gate Array(FPGA) is widely applied in the field of aerospace, whose anti-SEU(Single Event Upset) capability becomes more and more important. To improve anti-FPGA SEU capability, the registers of the circuit netlist are tripled and divided into three categories in this study. By the packing algorithm, the registers of triple modular redundancy are loaded into different configurable logic block. At the same time, the packing algorithm considers the effect of large fan-out nets. The experimental results show that the algorithm successfully realize the packing of the register of Triple Modular Redundancy(TMR). Comparing with Timing Versatile PACKing(TVPACK), the algorithm in this study is able to obtain a 11% reduction of the number of the nets in critical path, and a 12% reduction of the time delay in critical path on average when TMR is not considered. Especially, some critical path delay of circuit can be improved about 33%.