A high efficiency charge pump circuit for low power applications

作     者：冯鹏 李昀龙 吴南健 

作者机构：State Key Laboratory for Super Lattices and MicrostructuresInstitute of SemiconductorsChinese Academy of Sciences 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2010年第31卷第1期

页      面：88-92页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：supported by the Chinese National High-Tech Research and Development Program(No.2006AA04A108) the National Natural Science Foundation of China(No.2008AA010703) 

主　　题：high efficiency low power charge pump circuit high-voltage generator standard CMOS process 

摘      要：A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumpingstage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.