Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier

作     者：Chao WU Lu-ping XU Hua ZHANG Wen-bo ZHAO 

作者机构：School of Aerospace Science and Technology Xidian University 

出 版 物：《Frontiers of Information Technology & Electronic Engineering》 (信息与电子工程前沿（英文版）)

年 卷 期：2015年第16卷第8期

页      面：700-706页

核心收录：

学科分类：0711[理学-系统科学] 07[理学] 08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Project supported by the National Natural Science Foundation of China (No. 61474001) 

主　　题：Process-variation-robust Sense amplifier (SA) Replica bit-line (RBL) delay Timing variation 

摘      要：A multi-stage dual replica bit-line delay （MDRBD） technique is proposed for reducing access time by suppressing the sense-amplifier enable （SAE） timing variation of low voltage static randomaccess memory （SRAM） applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-fine （RBL） capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology （Taiwan Semiconductor Manufacturing Company, Taiwan）.