A Versatile 1.4-mW 6-bits CMOS ADC for Pulse-Based UWB Communication Systems

作     者：Saeed Ghamari Frederic Chastellain Cyril Botteron Christian Robert Pierre-André Farine 

作者机构：Electronics and Signal Processing Lab Ecole Polytechnique Fédérale de Lausanne Neuchatel 2000 Switzerland RUAG Space AG Zurich 8052 Switzerland 

出 版 物：《Journal of Electrical Engineering》 (电气工程（英文版）)

年 卷 期：2014年第2卷第3期

页      面：101-107页

学科分类：080802[工学-电力系统及其自动化] 0808[工学-电气工程] 08[工学] 

基　　金：The authors are grateful to the Swiss National Science Foundation (http://www.snsf.ch) who partially supported this work under grant 200021 146765/1 

主　　题：电气控制 控制理论 电气测量 集中参数 

摘      要：An ADC (analog to digital converter) using the low duty-cycle nature of pulse-based UWB (ultra wide-band) communications to reduce its power consumption is proposed. Implemented in CMOS (complementary metal-oxide-semiconductor) 180 nm technology, it can capture a 5 ns window at 4 GS/s each 100 ns, which corresponds to the acquisition of one UWB pulse at the pulse repetition rate of 10 Mpps (mega pulses per second). By using time-interleaved RSD (redundant signed digit) ADCs, the complete ADC occupies only 0.15 mm2 and consumes only 1.4 mW from a 1.8 V power supply. The ADC can be operated in two modes using the same core circuits (OTA (operational transconductance amplifier), comparators, etc.). The first mode is the standard RSD doubling mode, while the second mode allows improving the signal-to-noise ratio by adding coherently the transmitted pulses of one symbol. For example, for audio applications, a 300 kbps data rate and processing gain up to 15 dB can be achieved at a clock frequency of 10 MHz.