A novel noise optimization technique for inductively degenerated CMOS LNA

作     者：耿志卿 王海永 吴南健 

作者机构：State Key Laboratory for Superlattices and MicrostructuresInstitute of Semiconductors Chinese Academy of Sciences 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2009年第30卷第10期

页      面：137-142页

核心收录：

学科分类：081901[工学-采矿工程] 0819[工学-矿业工程] 080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：supported by the National Natural Science Foundation of China(No.90607007) the State Key Development Program for Basic Research of China(Nos.2006AA04A108,2008AA010703) 

主　　题：low noise optimization noise factor 

摘      要：This paper proposes a novel noise optimization *** technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier（LNA）circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation,respectively,by mathematical analysis and reasonable approximation *** circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed *** design a 1.8 GHz LNA in a TSMC 0.25 μm CMOS *** measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW,demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.