Design and simulation of a Torus topology for network on chip

作     者：Wu Chang Li Yubai Chai Song 

作者机构：DSP Lab School of Communication and Information Engineering~Univ. of Electronic Science and Technology of China Chengdu 610054 P. R. China 

出 版 物：《Journal of Systems Engineering and Electronics》 (系统工程与电子技术（英文版）)

年 卷 期：2008年第19卷第4期

页      面：694-701页

核心收录：

学科分类：0808[工学-电气工程] 07[理学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080203[工学-机械设计及理论] 070104[理学-应用数学] 0802[工学-机械工程] 0701[理学-数学] 0811[工学-控制科学与工程] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：the National Natural Science Fundation of China (60575031). 

主　　题：network on chip Torus route System C simulation 

摘      要：Aiming at the applications of NOC （network on chip） technology in rising scale and complexity on chip systems, a Torus structure and corresponding route algorithm for NOC is proposed. This Torus structure improves traditional Torus topology and redefines the denotations of the routers. Through redefining the router denotations and changing the original router locations, the Torus structure for NOC application is reconstructed. On the basis of this structure, a dead-lock and live-lock free route algorithm is designed according to dimension increase. System C is used to implement this structure and the route algorithm is simulated. In the four different traffic patterns, average, hotspot 13%, hotspot 67% and transpose, the average delay and normalization throughput of this Torus structure are evaluated. Then, the performance of delay and throughput between this Torus and Mesh structure is compared. The results indicate that this Torus structure is more suitable for NOC applications.