A time-domain digitally controlled oscillator composed of a free running ring oscillator and flying-adder

作     者：刘渭 李伟 任鹏 林庆龙 张盛东 王阳元 

作者机构：Institute of MicroelectronicsPeking University Shenzhen Graduate SchoolPeking University Semiconductor Manufacturing International Corporation 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2009年第30卷第9期

页      面：70-74页

核心收录：

学科分类：080904[工学-电磁场与微波技术] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0825[工学-航空宇航科学与技术] 

主　　题：all-digital phase-locked loops clock generator digitally controlled oscillator flying-adder free-running ring oscillator 

摘      要：A time-domain digitally controlled oscillator （DCO） is proposed. The DCO is composed of a free-running ring oscillator （FRO） and a two lap-selectors integrated flying-adder （FA）. With a coiled cell array which allows uniform loading capacitances of the delay cells, the FRO produces 32 outputs with consistent tap spacing for the FA as reference clocks. The FA uses the outputs from the FRO to generate the output of the DCO according to the control number, resulting in a linear dependence of the output period, instead of the frequency on the digital controlling word input. Thus the proposed DCO ensures a good conversion linearity in a time-domain, and is suitable for time-domain all-digital phase locked loop applications. The DCO was implemented in a standard 0.13μm digital logic CMOS process. The measurement results show that the DCO has a linear and monotonic tuning curve with gain variation of less than 10%, and a very low root mean square period jitter of 9.3 ps in the output clocks. The DCO works well at supply voltages ranging from 0.6 to 1.2 V, and consumes 4 mW of power with 500 MHz frequency output at 1.2 V supply voltage.