Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder

作     者：Wan-yi LI Lu YU 

作者机构：Institute of Information and Communication Engineering Zhejiang University Hangzhou 310027 China 

出 版 物：《Journal of Zhejiang University-Science A(Applied Physics & Engineering)》 (浙江大学学报（英文版）A辑（应用物理与工程）)

年 卷 期：2008年第9卷第12期

页      面：1638-1643页

核心收录：

学科分类：0810[工学-信息与通信工程] 08[工学] 0805[工学-材料科学与工程（可授工学、理学学位）] 081001[工学-通信与信息系统] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Project (No. 20051321B01) supported by the Science and Technology Development Project of Hangzhou China 

主　　题：VLSI体系结构 插值 高清晰度电视 编码 

摘      要：In this paper, we propose an effective VLSI architecture of sub-pixel interpolation for motion compensation in the AVS HDTV decoder. To utilize the similar arithmetical operations of 15 luma sub-pixel positions, three types of interpolation filters are proposed. A simplified multiplier is presented due to the limited range of input in the chroma interpolation process. To improve the processing throughput, a parallel and pipelined computing architecture is adopted. The simulation results show that the proposed hardware implementation can satisfy the real-time constraint for the AVS HDTV (1920×1088) 30 fps decoder by operating at 108 MHz with 38.18k logic gates. Meanwhile, it costs only 216 cycles to accomplish one macroblock, which means the B frame sub-pixel interpolation can be realized by using only one set of the proposed architecture under real-time constraints.