Hardware Performance Evaluation of SHA-3 Candidate Algorithms

作     者：Yaser Jararweh Lo’ai Tawalbeh Hala Tawalbeh Abidalrahman Moh’d 

作者机构：Computer Science Department Jordan University of Science and Technology(CHiS) Irbid Jordan Director of Cryptographic Hardware and Information Security Lab (CHiS) Computer Engineering DepartmentJordan University of Science and Technology Irbid Jordan Engineering Mathematics & Internetworking Dalhousie University Halifax Canada 

出 版 物：《Journal of Information Security》 (信息安全（英文）)

年 卷 期：2012年第3卷第2期

页      面：69-76页

学科分类：081203[工学-计算机应用技术] 08[工学] 0835[工学-软件工程] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：Information Security Secure Hash Algorithm (SHA) Hardware Performance FPGA 

摘      要：Secure Hashing Algorithms (SHA) showed a significant importance in today’s information security applications. The National Institute of Standards and Technology (NIST), held a competition of three rounds to replace SHA1 and SHA2 with the new SHA-3, to ensure long term robustness of hash functions. In this paper, we present a comprehensive hardware evaluation for the final round SHA-3 candidates. The main goal of providing the hardware evaluation is to: find the best algorithm among them that will satisfy the new hashing algorithm standards defined by the NIST. This is based on a comparison made between each of the finalists in terms of security level, throughput, clock frequancey, area, power consumption, and the cost. We expect that the achived results of the comparisons will contribute in choosing the next hashing algorithm (SHA-3) that will support the security requirements of applications in todays ubiquitous and pervasive information infrastructure.