Error Correction Circuit for Single-Event Hardening of Delay Locked Loops

作     者：S. Balaji S. Ramasamy S. Balaji;S. Ramasamy

作者机构：Department of ECE Loyola-ICAM College of Engineering and Technology Tamilnadu India Department of ECE RMK Engineering College Tamilnadu India 

出 版 物：《Circuits and Systems》 (电路与系统（英文）)

年 卷 期：2016年第7卷第9期

页      面：2437-2442页

学科分类：08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：Delay-Locked Loop Single Event Transients Error Correction Circuit 

摘      要：In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm2/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.