A 0.5-V, 1.2-GS/s, 6-Bit Flash ADC Using Temporarily-Boosted Comparator

作     者：Kenichi Ohhata Masataro Iwamoto Naoto Yamaguchi 

作者机构：Department of Electrical and Electronics Engineering Kagoshima University Kagoshima Japan 

出 版 物：《Circuits and Systems》 (电路与系统（英文）)

年 卷 期：2015年第6卷第8期

页      面：179-187页

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：ADC Low Voltage Flash Comparator Calibration 

摘      要：A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V.