Current Mode Logic Testing of XOR/XNOR Circuit: A Case Study

作     者：Mona M. Fouad Hassanein H. Amer Ahmed H. Madian Mohamed B. Abdelhalim 

作者机构：College of Computing and Information Technology AASTMT Cairo Egypt Electronics Engineering Department American University in Cairo Cairo Egypt Faculty of Engineering Cairo University Cairo Egypt Radiation Engineering Department NCRRT Cairo Egypt 

出 版 物：《Circuits and Systems》 (电路与系统（英文）)

年 卷 期：2013年第4卷第4期

页      面：364-368页

学科分类：1002[医学-临床医学] 100214[医学-肿瘤学] 10[医学] 

主　　题：Current Mode Logic (CML) CMOS Testing Stuck-At Faults 

摘      要：This paper investigates the issue of testing Current Mode Logic (CML) gates. A three-bit parity checker is used as a case study. It is first shown that, as expected, the stuck-at fault model is not appropriate for testing CML gates. It is then proved that switching the order in which inputs are applied to a gate will affect the minimum test set;this is not the case in conventional voltage mode gates. Both the circuit output and its inverse have to be monitored to reduce the size of the test set.