Fault Tolerance Limits and Input Stimulus Selection Using an Implemented FPGA-Based Testing System
Fault Tolerance Limits and Input Stimulus Selection Using an Implemented FPGA-Based Testing System作者机构：Department of Electronic Engineering T.E Alexander Technological & Educational Institute of Thessaloniki Thessaloniki Greece
出 版 物：《Journal of Computer and Communications》 (电脑和通信（英文）)
年 卷 期：2014年第2卷第13期
页 面：18-24页
学科分类：1002[医学-临床医学] 100214[医学-肿瘤学] 10[医学]
主 题：Fault Detection External Testing System
摘 要：In this paper, the selection of fault tolerance limits and input stimulus using an implemented adaptive FPGA-based testing system based on a method utilizing wavelet transformation of the current waveforms is presented. The testing scheme is innovative because it offers the ability of applying different input stimulus signals with respect to the requirements of the examined circuit. Moreover, the method used is simple, offers a single-point test measurement solution and may easily be adapted to test various other analog and mixed-signal systems. Experimental results are presented showing the advantages of the proposed testing scheme.
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