Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process

作     者：徐步陆 邵博闻 林霞 易伟 刘芸 

作者机构：Shanghai Silicon Intellectual Property Exchange 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2010年第31卷第9期

页      面：99-103页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0805[工学-材料科学与工程（可授工学、理学学位）] 0703[理学-化学] 0702[理学-物理学] 

主　　题：current-steering digital-to-analog converter low power matching error current source array mixedsignal integrated circuits 

摘      要：Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q;random walk NMOS current source layout routing method,a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-μm CMOS *** total consumption is only 10 mW from a single 1.2-V power supply,and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, *** the output signal frequency is 1-5 MHz at 100-MSPS sampling rate,the SFDR is measured to be 70 *** die area is about 0.2 mm;.