High-stage analog accumulator for TDI CMOS image sensors

作     者：李建新 黄福军 宗勇 高静 

作者机构：School of Electronic Information Engineering Tianjin University 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2016年第37卷第2期

页      面：105-115页

核心收录：

学科分类：080202[工学-机械电子工程] 08[工学] 0802[工学-机械工程] 

基　　金：supported by the National Natural Science Foundation of China(Nos.61404090 61434004) 

主　　题：accumulator signal-to-noise ratio (SNR) time delay integration (TDI) CMOS image sensor (CIS) 

摘      要：The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is em- ployed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature （PVT） variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure.