Parity generator and parity checker in the modified trinary number system using savart plate and spatial light modulator

作     者：Amal K Ghosh 

作者机构：Department of Applied Electronics & Instrumentation Engineering Netaji Subhash Engineering College Techno City Garia Kolkata 700152 India 

出 版 物：《Optoelectronics Letters》 (光电子快报（英文版）)

年 卷 期：2010年第6卷第5期

页      面：325-327页

核心收录：

学科分类：0810[工学-信息与通信工程] 0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 080902[工学-电路与系统] 08[工学] 0805[工学-材料科学与工程（可授工学、理学学位）] 081001[工学-通信与信息系统] 0702[理学-物理学] 

主　　题：空间光调制器 通讯系统 奇偶 发生器 三元 修改 检查 校验 

摘      要：The parity generators and the checkers are the most important circuits in communication systems. With the development of multi-valued logic (MVL), the proposed system with parity generators and checkers is the most required using the recently developed optoelectronic technology in the modified trinary number (MTN) system. This system also meets up the tremendous needs of speeds by exploiting the savart plates and spatial light modulators (SLM) in the optical tree architecture (OTA).