A Self-Biased Low-Jitter Process-Insensitive Phase-Locked Loop for 1.25Gb/s-6.25Gb/s SerDes

作     者：YUAN Hengzhou GUO Yang LIU Yao LIANG Bin GUO Qiancheng 

作者机构：College of Computer ScienceNational University of Defense Technology 

出 版 物：《Chinese Journal of Electronics》 (电子学报(英文))

年 卷 期：2018年第27卷第5期

页      面：1009-1014页

核心收录：

学科分类：11[军事学] 0810[工学-信息与通信工程] 1105[军事学-军队指挥学] 08[工学] 081002[工学-信号与信息处理] 110503[军事学-军事通信学] 

基　　金：supported by the National Natural Science Foundation of China(No.61772540) 

主　　题：Phase-locked loop(PLL) Self-biased Low-jitter Process-insensitive Serializer-deserializer 

摘      要：The paper presents a fully integrated multiphase output low-jitter CMOS phase-locked loop for1.25 Gb/s to 6.25 Gb/s wireline Ser Des transmitter clocking. The self-biased bandwidth technology with simplified structure is applied to reduce the sensitivity to process variations. A differential Charge pump(CP) which is suitable for low power supply and process migration is proposed. An accelerator is built to avoid the disadvantage of great damping factor. Self-adaptive frequency dividers are used to improve power efficiency. The simulation results under 65 nm and 55 nm process almost maintain almost the same jitter performance and show the high process insensitivity and good jitter performance.