Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement

作     者：S.Poorvasha B.Lakshmi 

作者机构：School of Electronics Engineering VIT University 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2018年第39卷第5期

页      面：30-40页

核心收录：

学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0805[工学-材料科学与工程（可授工学、理学学位）] 0703[理学-化学] 0702[理学-物理学] 

基　　金：Project supported by the Department of Science and Technology Government of India under SERB Scheme(No.SERB/F/2660) 

主　　题：double gate tunnel FETs gate drain overlap unity gain cut off frequency maximum oscillation frequency Y parameters modeling 

摘      要：In this paper,RF performance analysis of In As-based double gate（DG）tunnel field effect transistors（TFETs）is investigated in both qualitative and quantitative fashion.This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters,unity gain cut-off frequency（f_t）,maximum oscillation frequency（f_（max））,intrinsic gain and admittance（Y）parameters.An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs.Higher ON-current（ION）of about 0.2 mA and less leakage current（IOFF）of 29 f A is achieved for DG TFET with gate-drain overlap.Due to increase in transconductance（g_m）,higher ft and intrinsic gain is attained for DG TFET with gate-drain overlap.Higher f_（max） of 985 GHz is obtained for drain doping of 5×10^（17）cm^（-3） because of the reduced gate-drain capacitance（C_（gd））with DG TFET with gate-drain overlap.In terms of Y-parameters,gate oxide thickness variation offers better performance due to the reduced values of Cgd.A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters.The simulation results are compared with this numerical model where the predicted values match with the simulated values.