High power-efficient asynchronous SAR ADC for IoT devices

作     者：Beichen Zhang Bingbing Yao Liyuan Liu Jian Liu Nanjian Wu 

作者机构：Institute of SemiconductorsChinese Academy of Sciences University of Chinese Academy of Sciences 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2017年第38卷第10期

页      面：2-8页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：SAR ADC asynchronous bootstrapped switch dynamic logic power efficiency 

摘      要：This paper presents a power-efficient 100-MS/s,10-bit asynchronous successive approximation register（SAR） *** includes an on-chip reference buffer and the total power dissipation is 6.8 *** achieve high performance with high power-efficiency in the proposed ADC,bootstrapped switch,redundancy,set-and-down switching approach,dynamic comparator and dynamic logic techniques are *** prototype was fabricated using 65 nm standard CMOS *** a 1.2-V supply and 100 MS/s,the ADC achieves an SNDR of 56.2 dB and a SFDR of 65.1 *** ADC core consumes only 3.1 mW,resulting in a figure of merit（FOM） of 30.27 fJ/conversionstep and occupies an active area of only 0.009 mm^2.