FPGA Based Wireless Multi-Node Transceiver and Monitoring System
FPGA Based Wireless Multi-Node Transceiver and Monitoring System作者机构：Electrical ＆ Electronics Engineering Faculty Ege University Izmir 35100 Turkey Electrical ＆ Electronics Engineering Department Engineering Faculty Abdullah Gul University Kayseri 38039 Turkey
出 版 物：《Journal of Mathematics and System Science》 (数学和系统科学（英文版）)
年 卷 期：2012年第2卷第1期
页 面：53-57页
学科分类：080904[工学-电磁场与微波技术] 0810[工学-信息与通信工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 080401[工学-精密仪器及机械] 0804[工学-仪器科学与技术] 080402[工学-测试计量技术及仪器] 0838[工学-公安技术] 081001[工学-通信与信息系统]
主 题：FPGA PicoBlaze RF multi-node wireless transceiver
摘 要：In recent years the variety and complexity of Wireless Sensor Network （WSN） applications, the nodes and the functions they are expected to perform have increased immensely. This poses the question of reducing the time from initial design of WSN applications to their implementation as a major research topic. RF communication programs for WSN nodes are generally written on microcontroller units （MCUs） for universal asynchronous receiver/transmitter （UART） data communication, however nowadays radio frequency （RF） designs based on field-programmable gate array （FPGA） have emerged as a very powerful alternative, due to their parallel data processing ability and software reconfigurability. In this paper, the authors present a prototype of a flexible multi-node transceiver and monitoring system. The prototype is designed for time-critical applications and can be also reconfigured for other applications like event tracking. The processing power of FPGA is combined with a simple communication protocol. The system consists of three major parts： wireless nodes, the FPGA and display used for visualization of data processing. The transmission protocol is based on preamble and synchronous data transmission, where the receiver adjusts the receiving baud rate in the range from min. 300 to max. 2400 bps. The most important contribution of this work is using the virtual PicoBlaze Soft-Core Processor for controlling the data transmission through the RF modules. The proposed system has been evaluated based on logic utilization, in terms of the number of slice flip flops, the number of 4 input LUTs （Look-Up Tables） and the number of bonded lOBs （Input Output Blocks）. The results for capacity usage are very promising as compared to other similar research.
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