High-Throughput Area-Efficient Processor for Cryptography

作     者：HUO Yuanhong LIU Dake 

作者机构：School of Computer Science and Technology Beijing Institute of Technology School of Information and Electronics Beijing Institute of Technology 

出 版 物：《Chinese Journal of Electronics》 (电子学报(英文))

年 卷 期：2017年第26卷第3期

页      面：514-521页

核心收录：

学科分类：07[理学] 070104[理学-应用数学] 0701[理学-数学] 

基　　金：supported by the National High-Tech Research and Development Program(863 Program)of China(No.2014AA01A705) 

主　　题：ASIP(Application specific instruction set processor) Cryptographic processor VLSI(Very largescale integration) Cryptography 

摘      要：Cryptography circuits for portable electronic devices provide user authentication and secure data *** circuits should,achieve high performance,occupy small chip area,and handle several cryptographic *** paper proposes a highperformance ASIP(Application specific instruction set processor)for five standard cryptographic algorithms including both block ciphers(AES,Camellia,and ARIA)and stream ciphers(ZUC and SNOW 3G).The processor reaches ASIC-like performance such as 11.6 Gb/s for AES encryption,16.0 Gb/s for ZUC,and 32.0 Gb/s for SNOW3G,etc under the clock frequency of 1.0 GHz with the area consumption of 0.56 mm2(65 nm).Compared with stateof-the-art VLSI designs,our design achieves high performance,low silicon cost,low power consumption,and sufficient *** its programmability,our design can offer algorithm modification when an algorithm supported is unfortunately cracked and invalid to *** product lifetime of our design can thus be extended.