Ultra-Low Power Pipeline Structure Exploiting Noncritical Stage with Circuit-Level Timing Speculation

作     者：Tao Luo Ya-Juan He Ping Luo Yan-Ming He Feng Hu 

作者机构：the School of Microelectronics and Solid-State Electronics University of Electronic Science and Technology of China 

出 版 物：《Journal of Electronic Science and Technology》 (电子科技学刊（英文版）)

年 卷 期：2013年第11卷第3期

页      面：301-305页

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：supported by the Important National S&T Special Project of China under Grant No.2011ZX01034-002-001-2 the Fundamental Research Funds for the Central Universities under Grant No.ZYGX2009J026 

主　　题：Index Terms---Adaptive circuits dynamic voltagescaling exploiting noncritical stage ultra-low power. 

摘      要：With the increase of the clock frequency and silicon integration, power aware computing has become a critical concern in the design of the embedded processor and system-on-chip （SoC）. Dynamic voltage scaling （DVS） is an effective method for low-power designs. However, traditional DVS methods have two deficiencies. First, they have a conservative safety margin which is not necessary for most of the time. Second, they are exclusively concerned with the critical stage and ignore the significant potential free slack time of the noncritical stage. These factors lead to a large amount of power waste. In this paper, a novel pipeline structure with ultra-low power consumption is proposed. It cuts off the safety margin and takes use of the noncritical stages at the same time. A prototype pipeline is designed in 0.13 μm technology and analyzed. The result shows that a large amount of energy can be saved by using this structure. Compared with the fixed voltage case, 50% of the energy can be saved, and with respect to the traditional adaptive voltage scaling design, 37.8% of the energy can be saved.