Research and Design of Reconfigurable Matrix Multiplication over Finite Field in VLIW Processor

作     者：Yang Su Xiaoyuan Yang Yuechuan Wei 

作者机构：Department of Electronic Technology Engineering University of PAP State Key Laboratory of Cryptology P. O. Box 5159 Beijing 100878 China 

出 版 物：《China Communications》 (中国通信（英文版）)

年 卷 期：2016年第13卷第10期

页      面：222-232页

核心收录：

学科分类：08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：supported in part by open project foundation of State Key Laboratory of Cryptology National Natural Science Foundation of China (NSFC) under Grant No. 61272492, No. 61572521 and No. 61309008 Natural Science Foundation for Young of Shaanxi Province under Grant No. 2013JQ8013 

主　　题：cryptography reconfigurable matrix multiplication research and design dedicated instruction VLIW processor 

摘      要：Matrix multiplication plays a pivotal role in the symmetric cipher algorithms, but it is one of the most complex and time consuming units, its performance directly affects the efficiency of cipher algorithms. Combined with the characteristics of VLIW processor and matrix multiplication of symmetric cipher algorithms, this paper extracted the reconfigurable elements and analyzed the principle of matrix multiplication, then designed the reconfigurable architecture of matrix multiplication of VLIW processor further, at last we put forward single instructions for matrix multiplication between 4×1 and 4×4 matrix or two 4×4 matrix over GF(2~8), through the instructions extension, the instructions could support larger dimension operations. The experiment shows that the instructions we designed supports different dimensions matrix multiplication and improves the processing speed of multiplication greatly.