Configurable Floating-Point FFT Accelerator on FPGA Based Multiple-Rotation CORDIC

作     者：CHEN Jiyang LEI Yuanwu PENG Yuanxi HE Tingting DENG Ziye 

作者机构：College of ComputerNational University of Defense and Technology (NUDT) 

出 版 物：《Chinese Journal of Electronics》 (电子学报(英文))

年 卷 期：2016年第25卷第06期

页      面：1063-1070页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：supported by Aerospace Science Fund of China(No.2013ZC88003) the National Natural Science Foundation of China(No.61402499) 

主　　题：Fast Fourier transform(FFT) Coordinate rotation digital computer(CORDIC) FPGA Floating-point 

摘      要：Fast Fourier transform(FFT) accelerator and Coordinate rotation digital computer(CORDIC) algorithm play important roles in signal processing. We propose a configurable floating-point FFT accelerator based on CORDIC rotation, in which twiddle direction prediction is presented to reduce hardware cost and twiddle angles are generated in real time to save memory. To finish CORDIC rotation efficiently, a novel approach in which segmentedparallel iteration and compress iteration based on CSA are presented and redundant CORDIC is used to reduce the latency of each iteration. To prove the efficiency of our FFT accelerator, four FFT accelerators are prototyped into a FPGA chip to perform a batch-FFT. Experimental results show that our structure, which is composed of four butterfly units and finishes FFT with the size ranging from 64 to8192 points, occupies 33230(3%) REGs and 143006(30%)LUTs. The clock frequency can reach 122 MHz. The resources of double-precision FFT is only about 2.5 times of single-precision while the theoretical value is 4. What s more, only 13331 cycles are required to implement 8192-points double-precision FFT with four butterfly units in parallel.