The Design and Implementation of a Very Fast Experimental Pipelining Computer
作者机构：Institute of Computing Technology Academia Sinica
出 版 物：《Journal of Computer Science and Technology》 (计算机科学技术学报(英文版))
年 卷 期：1988年第3卷第1期
页 面：1-6页
学科分类：1002[医学-临床医学] 100214[医学-肿瘤学] 10[医学]
基 金：This project is partly supported by National Natural Science Foundation of China
主 题：The Design and Implementation of a Very Fast Experimental Pipelining Computer line
摘 要：The high speed potential of *** can be exploited by shortening the pipeline clock *** there are some factors which dominate the shortening,the design of an experimental computeremploys the principle of maximum time difference at the system level to determine the clock period and theintegrated consideration of architecture,logic design and engineering layout to achieve a system clock periodof 9.8 ns using conventional ECL chips of 2ns gate *** multiplier in this model,which is constructedwith 0.7 ns gate delay chips,can work at a cloek period of 5.5 ns.
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