On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time

作     者：WANG Fei WANG Da YANG Haigang XIE Xianghui FAN Dongrui 

作者机构：System on Programmable Chip Research Department IE CAS State Key Laboratory of Computer Architecture ICT CAS 

出 版 物：《Chinese Journal of Electronics》 (电子学报(英文))

年 卷 期：2016年第25卷第1期

页      面：64-70页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：supported by the National Basic Research Program of China(973 Program)(No.2011CB302501) the National High Technology Research and Development Program of China(863 Program)(No.2015AA01A301) the National Science Foundation of China(No.61204047,No.61204045,No.61332009) the Major Project of China(No.2013ZX0102-8001-001-001) Beijing Natural Science Foundation(No.4143060) 

主　　题：FPGA test Test configuration bitstream Design-for-testability 

摘      要：Statistics shows that over 95% of FPGA manufacturing test time is spent on loading test configuration bitstreams. Reducing the test time that spent on loading test configuration bitstreams could significantly reduce FPGA test time. A new approach which can significantly reduce the FPGA test time is presented. Experimental results show that the proposed technique can at least reduce the configuration loading time by 96%, while getting 100%test coverage with less than 1.2% hardware overhead.