A high speed multi-level-parallel array processor for vision chips

作     者：SHI Cong YANG Jie WU NanJian WANG ZhiHua 

作者机构：State Key Laboratory for Superlattices and MicrostructuresInstitute of SemiconductorsChinese Academy of Sciences Department of Electronic EngineeringTsinghua University Institute of MicroelectronicsTsinghua University 

出 版 物：《Science China(Information Sciences)》 (中国科学:信息科学(英文版))

年 卷 期：2014年第57卷第6期

页      面：211-222页

核心收录：

学科分类：08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：supported by National Natural Science Foundation of China(Grant Nos.60976023,61234003) Special Funds for Major State Basic Research Project of China(Grant No.2011CB932902) 

主　　题：vision chip array processor multi-level-parallel high speed image processing face detection 

摘      要：This paper proposes a high speed multi-level-parallel array processor for programmable vision *** processor includes 2-D pixel-parallel processing element(PE)array and 1-D row-parallel row processor(RP)*** two arrays both operate in a single-instruction multiple-data(SIMD)fashion and share a common instruction *** sizes of the arrays are scalable according to dedicated *** PE array,each PE can communicate not only with its nearest neighbor PEs,but also with the next near neighbor PEs in diagonal *** connection can help to speed up local operations in low-level image *** the other hand,global operations in mid-level processing are accelerated by the skipping chain and binary boosters in RP *** array processor was implemented on an FPGA device,and was successfully tested for various algorithms,including real-time face detection based on PPED *** results show that the image processing speed of proposed processor is much higher than that of the state-of-the-arts digital vision chips.