Nonlinearity Calibration for Pipelined ADCs by Splitting Capacitors with Self-Tracking Comparator Thresholds
Nonlinearity Calibration for Pipelined ADCs by Splitting Capacitors with Self-Tracking Comparator Thresholds作者机构：Center for Analog/RF IC School of Microelectronics Shanghai Jiao Tong University
出 版 物：《Chinese Journal of Electronics》 (电子学报(英文))
年 卷 期：2015年第24卷第3期
页 面：474-479页
核心收录：
学科分类：0808[工学-电气工程] 0809[工学-电子科学与技术（可授工学、理学学位）] 080902[工学-电路与系统] 08[工学] 0701[理学-数学]
主 题：Pipelined ADC Nonlinearity Background calibration Residue amplifier
摘 要：A digital background calibration technique which mainly corrects nonlinear errors of residue amplifiers in pipelined analog-to-digital converters(ADCs) is presented. The proposed technique extracts the nonlinear errors by splitting sampling capacitors and inserting two extra comparators, and is highly effective as long as the input signal is busy. The method of self-tracking comparator thresholds is proposed to reduce the time of convergence with low complexity for any bit cases in a pipelined ADC.Both measurement and correction are processed in digital domain. After calibration, the behavioral simulation shows that the Signal-to-noise-and-distortion ratio(SNDR) is raised from 55.4d B to 90.2d B and the Spurious-free dynamic range(SFDR) is improved from 61.6d B to 102 d B in a 16-bit prototype pipelined ADC with 0.5% capacitor mismatches and 4.5% gain compression of the residue amplifier.
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