A novel CMOS charge-pump circuit with current mode control 110mA at 2.7V for telecommunication systems

作     者：Salahddine Krit Hassan Qjidaa Imad El Affar Yafrah Khadija Ziani Messghati Yassir El-Ghzizal 

作者机构：Faculty of Sciences Dhar El MehrazLaboratory of ElectronicSignal-Systymes and Informatic(LESSI)FesMorocco 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2010年第31卷第4期

页      面：57-61页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：switch capacitor charge pump voltage doubler power consumption 

摘      要：This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm^2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.