Smaller, faster, lower-power analog RRAM matrix computing circuits without performance compromise
作者机构：School of Integrated Circuits Peking University Institute for Artificial Intelligence Peking University Beijing Advanced Innovation Center for Integrated Circuits
出 版 物：《Science China(Information Sciences)》 (中国科学:信息科学(英文版))
年 卷 期：2025年
核心收录：
学科分类：08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）]
基 金：supported by National Key R&D Program of China (Grant No. 2020YFB2206001) National Natural Science Foundation of China (Grant Nos. 62004002, 92064004, 61927901) 111 Project (Grant No. B18001)
摘 要：Recently, the analog matrix computing (AMC) concept has been proposed for fast, efficient matrix operations, by configuring global feedback loops with crosspoint resistive memory arrays and operational amplifiers (OAs). The implementation of a general real-valued matrix (containing both positive and negative elements) is enabled by using a set of analog inverters,which, however, is considered inefficient regarding circuit compactness, power consumption, and temporal response. Here, with the assistance of the conductance compensation (CC) strategy to take full advantage of the inherent differential inputs of OAs,new AMC circuits without analog inverters are designed. Such a design saves the area occupation and power dissipation of analog inverters, and thus turns to be smaller and lower-power. Simulation results reveal that the new circuit also shows a faster response towards the steady state, thanks to the reduction of poles in the circuit, which, again, is contributed by the elimination of analog inverters. Along with all of these benefits, extensive simulations demonstrate that the CC-AMC circuits do not compromise the computing performance in terms of relative error caused by various non-ideal factors in the circuit.
同方期刊数据库