An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network
An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network作者机构：Department of Computer National University of Defense Technology
出 版 物：《Science China(Information Sciences)》 (中国科学:信息科学(英文版))
年 卷 期：2013年第56卷第7期
页 面：239-258页
核心收录：
学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学]
基 金：supported in part by National Basic Research Program (Grant No. 2007CB310901) National Science Foundation of China (Grant Nos. 60903039, 61103188, 61025009) Education Foundation of China(Grant No. 20094307120012)
主 题：on-chip network model performance analysis
摘 要：An accurate and highly-efficient analysis approach is crucial for a designer to evaluate the performance of on-chip networks. To this end, the novel M/G/1/N queuing models that capture various blocking phenomenon of the wormhole switching router are presented to compute the average waiting time accurately. With the M/G/1/N queuing models, this paper then presents the performance analysis algorithm to estimate some key metrics in terms of packet latency, buffer utilization, etc. The comparisons with SystemC simulated results show that the proposed approach with mean errors of 6.9% and 7.8% achieves the speedups of 117 and 101 for single-channel and multi-channel routers respectively. In our design methodology, this approach can direct NoC synthesis process effectively and then can be applied to multi-objective optimizations conveniently to find the best mappings.
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