A PLL Clock Frequency Multiplier Using Dynamic Current Matching Adaptive Charge-Pump and VCO Frequency Reuse

作     者：ZHANG Tao ZOU Xuecheng ZHAO Guangzhou SHEN Xubang 

作者机构：College of Information Science and Engineering Wuhan University of Science and Technology Wuhan 430070 Hubei China Department of Electronic Science and Technology Huazhong University of Science and Technology Wuhan 430074 Hubei China Institute of Pattern Recognition and Artifical Intelligence Huazhong University of Science and Technology Wuhan 430074 Hubei China Xi＇an Microelectronic Technology Institute Xi＇an 710054 Shaanxi China 

出 版 物：《Wuhan University Journal of Natural Sciences》 (武汉大学学报（自然科学英文版）)

年 卷 期：2007年第12卷第3期

页      面：491-495页

学科分类：08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Supported by the National Key Pre-Research Project of China (413010701-3) 

主　　题：low voltage different signal phase locked loop multiplier adaptive charge pump phase noise 

摘      要：A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .