A low-jitter low-power monolithically integrated optical receiver for SDH STM-16

作     者：CHEN YingMei , WANG ZhiGong & ZHANG Li Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China 

作者机构：Institute of RF- & OE-ICs Southeast University Nanjing China 

出 版 物：《Science China(Information Sciences)》 (中国科学:信息科学(英文版))

年 卷 期：2011年第54卷第6期

页      面：1293-1299页

核心收录：

学科分类：0810[工学-信息与通信工程] 08[工学] 081001[工学-通信与信息系统] 

基　　金：supported by the National Natural Science Foundation of China(Grant No.60976029) 

主　　题：optical receiver jitter preamplifier limiting amplifier clock and data recovery demultiplexer 

摘      要：A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25 μm CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-to-peak jitter of the recovered 625 MHz clock are 9.4 and 46.3 ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. In response to 2.5 Gb/s PRBS input data (2 23 1), the recovered and frequency divided 625 MHz clock has a phase noise of 83.8 dBc/Hz at 20 kHz offset and the 2.5 Gb/s PRBS data has been demultiplexed into four 625 Mb/s data. The power dissipation is only 0.3 W under a single 3.3 V supply (excluding output buffers).