Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance

作     者：董耀旗 孔蔚然 Nhan Do 王序伦 李荣林 

作者机构：Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Grace Semiconductor Manufacturing Corporation Graduate University of the Chinese Academy of Sciences Silicon Storage Technology Inc. 1171 Sonora CourtSunnyvale 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2010年第31卷第6期

页      面：74-77页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 07[理学] 070205[理学-凝聚态物理] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程（可授工学、理学学位）] 0702[理学-物理学] 

主　　题：split-gate flash endurance erase voltage 

摘      要：The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is *** optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.