Buffer planning for application-specific networks-on-chip design

作     者：YIN ShouYi1,2,LIU LeiBo1,2 & WEI ShaoJun1,2 1 Institute of Microelectronics,Tsinghua University,Beijing 100084,China 2 National Laboratory for Information Science and Technology,Tsinghua University,Beijing 100084,China 

作者机构：Institute of Microelectronics Tsinghua University Beijing China National Laboratory for Information Science and Technology Tsinghua University Beijing China 

出 版 物：《Science in China(Series F)》 (中国科学（F辑英文版）)

年 卷 期：2009年第52卷第4期

页      面：547-558页

核心收录：

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：Supported by the National Natural Science Foundation of China (Grant No. 60803018) 

主　　题：buffer planning networks-on-chip (NoC) design automation optimization 

摘      要：Networks-on-chip （NoC） is a promising communication architecture for next generation SoC. The size of buffer used in on-chip routers impacts the silicon area and power consumption of NoC dominantly. It is important to plan the total buffer-size and each router buffer-allocation carefully for an efficient NoC design. In this paper, we propose two buffer planning algorithms for application-specific NoC design. More precisely, given the traffic parameters and performance constraints of target application, the proposed algorithms automatically determine minimal buffer budget and assign the buffer depth for each input channel in different routers. The experimental results show that the proposed algorithms can significantly reduce total buffer usage and guarantee the performance requirements.