Design and implementation of a high-speed reconfigurable cipher chip

作     者：Gao Nana Li Zhancai Wang Qin 

作者机构：Information Technology School Beijing Univ. of Science & Technology Beijing 100083 P.R.China. 

出 版 物：《Journal of Systems Engineering and Electronics》 (系统工程与电子技术（英文版）)

年 卷 期：2006年第17卷第4期

页      面：712-716页

核心收录：

学科分类：11[军事学] 1105[军事学-军队指挥学] 0839[工学-网络空间安全] 08[工学] 110505[军事学-密码学] 081201[工学-计算机系统结构] 110503[军事学-军事通信学] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：reconfigurable cipher chip DES AES. 

摘      要：A reconfigurable cipher chip for accelerating DES is described, 3DES and AES computations that demand high performance and flexibility to accommodate large numbers of secure connections with heterogeneous clients. To obtain high throughput, we analyze the feasibility of high-speed reconfigurable design and find the key parameters affecting throughput. Then, the corresponding design, which includes the reconfignration analysis of algorithms, the design of reconfignrable processing units and a new reconfignrable architecture based on pipeline and parallel structure, are proposed. The implementation results show that the opcrating fiequency is 110 MHz and the throughput rate is 7 Gbps for DES, 2.3 Gbps for 3 DES and 1.4 Gbps for AES. Compared with the similar existing implementations, our design can achieve a higher performance.