Multi-bits error detection and fast recovery in RISC cores

作     者：王晶 杨星 赵元富 张伟功 申娇 邱柯妮 

作者机构：College of Information Engineering Capital Normal University Beijing Engineering Research Center of High Reliable Embedded System Beijing Microelectronics Technology Institute Beijing Key Laboratory of Electronic System Reliability and Prognostics 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2015年第36卷第11期

页      面：106-113页

核心收录：

学科分类：08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

主　　题：MBU SEU SET automatic recovery pipeline hardened 

摘      要：The particles-induced soft errors are a major threat to the reliability of microprocessors. Even worse,multi-bits upsets（MBUs） are ever-increased due to the rapidly shrinking feature size of the IC on a chip. Several architecture-level mechanisms have been proposed to protect microprocessors from soft errors, such as dual and triple modular redundancies（DMR and TMR）. However, most of them are inefficient to combat the growing multibits errors or cannot well balance the critical paths delay, area and power penalty. This paper proposes a novel architecture, self-recovery dual-pipeline（SRDP）, to effectively provide soft error detection and recovery with low cost for general RISC structures. We focus on the following three aspects. First, an advanced DMR pipeline is devised to detect soft error, especially MBU. Second, SEU/MBU errors can be located by enhancing self-checking logic into pipelines stage registers. Third, a recovery scheme is proposed with a recovery cost of 1 or 5 clock *** evaluation of a prototype implementation exhibits that the SRDP can successfully detect particle-induced soft errors up to 100% and recovery is nearly 95%, the other 5% will inter a specific trap.