An analytical model for Network-on-Chip with finite input buffer
An analytical model for Network-on-Chip with finite input buffer作者机构：Univ Elect Sci & Technol China Didital Signal Proc Lab Sch Commun & Informat Engn Chengdu 610054 Peoples R China
出 版 物：《Frontiers of Computer Science》 (中国计算机科学前沿（英文版）)
年 卷 期：2011年第5卷第1期
页 面：126-134页
核心收录：
学科分类：0821[工学-纺织科学与工程] 08[工学] 082101[工学-纺织工程] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）]
基 金：国家自然科学基金
主 题：analytical model finite buffer Network-on-Chip (NoC) queue system
摘 要：An analytical model is proposed for input buffer router architecture Network-on-Chip （NoC） with finite size buffers. The model is developed based on M/G/ 1/K queuing theory and takes into consideration the restriction of buffer sizes in NoC. It analyzes the packet＇s sojourn time in each buffer and calculates the packets average latency in NoC The validity of the model is verified through simulation. By comparing our analytical outcomes to the simulation results, we show that the proposed model successfully captures the performance characteristics of NoC, which provides an efficient performance analysis tool for NoC design.
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