A write buffer design based on stable and area-saving embedded SRAM for flash applications

作     者：CAO Hua Min HUO Zong Liang WANG Yu LI Ting LIU Jing JIN Lei JIANG Dan-Dan ZHANG Deng Jun LI Di LIU Ming 

作者机构：Institute of Microelectronics Chinese Academy of Sciences College of Communication Engineering Chengdu University of Information Technology Guangdong Berg Micro Co. Ltd. 

出 版 物：《Science China(Technological Sciences)》 (中国科学（技术科学英文版）)

年 卷 期：2015年第58卷第2期

页      面：357-361页

核心收录：

学科分类：08[工学] 081201[工学-计算机系统结构] 0822[工学-轻工技术与工程] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：supported by the MOST(Grant Nos.2010CB934200 and 2011CBA00600) the National Natural Science Foundation of China(Grant Nos.61176073 and 61221004) 

主　　题：write buffer embedded SRAM flash 65 nm technology 2 kb 128 Mb 

摘      要：This paper presents an embedded SRAM design for write buffer applications in flash *** write buffer is implemented with a newly proposed self-adaptive timing control circuit,an area-saving sense-latch circuit and 6 T SRAM cell units.A 2 kb SRAM macro with the area of 135μm×180μm is implemented in and applied to a 128 Mb NOR flash memory with the SMIC 65 nm NOR flash memory *** simulation and chip test results show that the SRAM write buffer is beneficial to high-density flash memory design.