Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF（2^m）

作     者：Ashutosh Kumar Singh Asish Bera Hafizur Rahaman Jimson Mathew Dhiraj K.Pradhan 

作者机构：CS Dept.School of EngineeringCurtin University of Technology School of VLSI TechnologyBengal Engg. & Sc. University Dept. of Information TechnologyBengal Engg. & Sc. University Computer Science Dept.University of Bristol 

出 版 物：《Journal of Electronic Science and Technology of China》 (中国电子科技（英文版）)

年 卷 期：2009年第7卷第4期

页      面：336-342页

学科分类：080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：Bit parallel error correction finitfield Reed-Solomon (RS) codes systolic very large scalintegration (VLSI) testing 

摘      要：An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.