A parallel and scalable digital architecture for training support vector machines

作     者：Kui-kang CAO Hai-bin SHEN Hua-feng CHEN 

作者机构：Institute of VLSI Design Zhejiang University Hangzhou 310027 China Zhejiang University of Media and Communications Hangzhou 310027 China 

出 版 物：《Journal of Zhejiang University-Science C(Computers and Electronics)》 (浙江大学学报C辑（计算机与电子（英文版）)

年 卷 期：2010年第11卷第8期

页      面：620-628页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

基　　金：Project (No.60720106003) supported by the National Natural Science Foundation of China 

主　　题：Support vector machine (SVM) Sequential minimal optimization (SMO) Field-programmable gate array (FPGA) Scalable architecture 

摘      要：To facilitate the application of support vector machines (SVMs) in embedded systems,we propose and test a parallel and scalable digital architecture based on the sequential minimal optimization (SMO) algorithm for training *** taking advantage of the mature and popular SMO algorithm,the numerical instability issues that may exist in traditional numerical algorithms are *** error cache updating task,which dominates the computation time of the algorithm,is mapped into multiple processing units working in *** results show that using the proposed architecture,SVM training problems can be solved effectively with inexpensive fixed-point arithmetic and good scalability can be *** architecture overcomes the drawbacks of the previously proposed SVM hardware that lacks the necessary flexibility for embedded applications,and thus is more suitable for embedded use,where scalability is an important concern.