Review on the Usage of Synchronous and Asynchronous FIFOs in Digital Systems Design

作     者：Dongwei Hu Yuejun Lei Linan Wang Dongwei Hu;Yuejun Lei;Linan Wang

作者机构：The 54th Research Institute of CETC Shijiazhuang China MUC School of Information Engineering Beijing China 

出 版 物：《Engineering（科研）》 (工程（英文）（1947-3931）)

年 卷 期：2024年第16卷第3期

页      面：61-82页

学科分类：0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：First-Input-First-Output System-on-Chip Network-on-Chip Advanced eXtensible Interface Asynchronous 

摘      要：First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.