Impact of Band-Engineering to Performance of High-k Multilayer Based Charge Trapping Memory

作     者：刘利芳 潘立阳 张志刚 许军 

作者机构：Institute of Microelectronics Tsinghua University Beijing 100084 Graduate School at Shenzhen Tsinghua University Shenzhen 518055 

出 版 物：《Chinese Physics Letters》 (中国物理快报（英文版）)

年 卷 期：2015年第32卷第8期

页      面：189-192页

核心收录：

学科分类：08[工学] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 

基　　金：Supported by the National Basic Research Program of China under Grant No 2011CBA00602 the National Key Scientific and Technological Project under Grant No 2013ZX01032001-001-003 

主　　题：Impact of Band-Engineering to Performance of High-k Multilayer Based Charge Trapping Memory HTH CTL Ta 

摘      要：Impact of band-engineering to the performance of charge trapping memory with HfO2/Ta2O5/HfO2 （HTH） as the charge trapping layer is investigated. Compared with devices with the same total HfO2 thickness, structures with Ta2O5 closer to substrates show larger program/erase window, because the 2nd HfO2 （next to blocking oxide） serving as part of blocking oxide reduces the current tunneling out of/in the charge trapping layer during program and erase. Moreover, trapped charge centroid is modulated and contributed more to the fiat-band voltage shift. Further experiments prove that devices with a thicker 2nd HfO2 layer exhibit larger saturate fiat-band shift in both program and erase operation. The optimized device achieves a 7 V memory window and good reliability characteristics.