Low working loss Si/4H-SiC heterojunction MOSFET with analysis of the gate-controlled tunneling effect

作     者：Hang Chen You-Run Zhang Hang Chen;You-Run Zhang

作者机构：State Key Laboratory of Electronic Thin Films and Integrated DevicesSchool of Integrated Circuit Science and EngineeringUniversity of Electronic Science and Technology of ChinaChengdu610054China 

出 版 物：《Journal of Electronic Science and Technology》 (电子科技学刊（英文版）)

年 卷 期：2023年第21卷第4期

页      面：35-47页

核心收录：

学科分类：080901[工学-物理电子学] 081704[工学-应用化学] 0809[工学-电子科学与技术（可授工学、理学学位）] 07[理学] 08[工学] 0817[工学-化学工程与技术] 080401[工学-精密仪器及机械] 0804[工学-仪器科学与技术] 0703[理学-化学] 0803[工学-光学工程] 070301[理学-无机化学] 

基　　金：the Major Science and Technology Program of Anhui Province under Grant No.2020b05050007 

主　　题：Heterojunction On-state resistance Silicon carbide(4H-SiC)trench metal-oxide-semiconductor field effect transistors(MOSFETs) Switching loss 

摘      要：A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.