咨询与建议

看过本文的还看了

相关文献

该作者的其他文献

文献详情 >Saturation thickness of stacke... 收藏

Saturation thickness of stacked SiO_(2)in atomic-layer-deposited Al_(2)O_(3)gate on 4H-SiC

作     者:邵泽伟 徐弘毅 王珩宇 任娜 盛况 Zewei Shao;Hongyi Xu;Hengyu Wang;Na Ren;Kuang Sheng

作者机构:College of Electrical EngineeringZhejiang UniversityHangzhou 310063China Hangzhou Global Scientific and Technological Innovation CenterZhejiang UniversityHangzhou 311215China 

出 版 物:《Chinese Physics B》 (中国物理B(英文版))

年 卷 期:2023年第32卷第8期

页      面:397-403页

核心收录:

学科分类:080903[工学-微电子学与固体电子学] 0809[工学-电子科学与技术(可授工学、理学学位)] 07[理学] 070205[理学-凝聚态物理] 08[工学] 080501[工学-材料物理与化学] 0805[工学-材料科学与工程(可授工学、理学学位)] 0702[理学-物理学] 

基  金:Project supported by the Key Area Research and Development Program of Guangdong Province of China(Grant No.2021B0101300005) the National Key Research and Development Program of China(Grant No.2021YFB3401603) 

主  题:4H-SiC SiO_(2)/Al_(2)O_(3)stacks saturation thickness dielectric breakdown 

摘      要:High-k materials as an alternative dielectric layer for SiC power devices have the potential to reduce interfacial state defects and improve MOS channel conduction ***,under identical conditions of gate oxide thickness and gate voltage,the high-k dielectric enables a greater charge accumulation in the channel region,resulting in a larger number of free electrons available for ***,the lower energy band gap of high-k materials leads to significant leakage currents at the interface with Si C,which greatly affects device *** inserting a layer of SiO_(2)between the high-k material and Si C,the interfacial barrier can be effectively widened and hence the leakage current will be *** this study,the optimal thickness of the intercalated SiO_(2)was determined by investigating and analyzing the gate dielectric breakdown voltage and interfacial defects of a dielectric stack composed of atomic-layer-deposited Al_(2)O_(3)layer and thermally nitride SiO_(2).Current-voltage and high-frequency capacitance-voltage measurements were performed on metal-oxide-semiconductor test structures with 35 nm thick Al_(2)O_(3)stacked on 1 nm,2 nm,3 nm,6 nm,or 9 nm thick nitride SiO_(2).Measurement results indicated that the current conducted through the oxides was affected by the thickness of the nitride oxide and the applied electric ***,a saturation thickness of stacked SiO_(2)that contributed to dielectric breakdown and interfacial band offsets was *** findings in this paper provide a guideline for the SiC gate dielectric stack design with the breakdown strength and the interfacial state defects considered.

读者评论 与其他读者分享你的观点

用户名:未登录
我的评分