An AND-LUT Based Hybrid FPGA Architecture

作     者：陈利光 来金梅 童家榕 Chen Liguang;Lai Jinmei;Tong Jiarong

作者机构：复旦大学微电子系上海200433 

出 版 物：《Journal of Semiconductors》 (半导体学报（英文版）)

年 卷 期：2007年第28卷第3期

页      面：398-403页

核心收录：

学科分类：080902[工学-电路与系统] 0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 

主　　题：hybrid FPGA AND-LUT array AND-OR array PLA LUT 

摘      要：A new hybrid FPGA architecture is proposed. The logic tile,which consists of a logic cluster and related connection boxes （CBs）, can be configured as either programmable logic arrays （PLAs） or look-up tables （LUTs）, This architecture can be classified as an AND-LUT array. PLAs are suitable for the implementation of high fan-in logic circuits, while LUTs are used to implement low fan-in logic circuits. As a result, the proposed hybrid FPGA architecture （HFA） is more flexible to improve logic density. Experiments based on MCNC benchmark circuits were performed in both the hybrid architecture and conventional LUT-based symmetrical FPGA architecture in term of area consumption. Preliminary results indicate that on average, the area is reduced by 46% using the new hybrid architecture.