A Fine-Grained Runtime Power/Performance Optimization Method for Processors with Adaptive Pipeline Depth

作     者：姚骏 Shinobu Miwa Hajime Shimada Shinji Tomita 

作者机构：Graduate School of Information ScienceNara Institute of Science and Technology School of EngineeringTokyo University of Agriculture and Technology Graduate School of InformaticsKyoto University Institute for Integrated Cell-Material SciencesKyoto University 

出 版 物：《Journal of Computer Science & Technology》 (计算机科学技术学报（英文版）)

年 卷 期：2011年第26卷第2期

页      面：292-301页

核心收录：

学科分类：08[工学] 080104[工学-工程力学] 0815[工学-水利工程] 081201[工学-计算机系统结构] 0812[工学-计算机科学与技术（可授工学、理学学位）] 0801[工学-力学（可授工学、理学学位）] 

基　　金：supported by VLSI Design and Education Center (VDEC) University of Tokyo with the collaboration with Synopsys Corporation 

主　　题：dynamic optimization energy saving fine-grained pipeline stage unification workload analysis 

摘      要：Recently, a method known as pipeline stage unification （PSU） has been proposed to alleviate the increasing energy consumption problem in modern microprocessors. PSU achieves a high energy efficiency by employing a changeable pipeline depth and its working scheme is eligible for a fine control method. In this paper, we propose a dynamic method to study fine-grained program interval behaviors based on some easy-to-get runtime processor metrics. Using this method to determine the proper PSU configurations during the program execution, we are able to achieve an averaged 13.5% energydelay-product （EDP） reduction for SPEC CPU2000 integer benchmarks, compared to the baseline processor. This value is only 0.14% larger than the theoretically idealized controlling. Our hardware synthesis result indicates that the proposed method can largely decrease the hardware overhead in both area and delay costs, as compared to a previous program study method which is based on working set signatures.