Optimized Power Factor Correction for High Speed Switched Reluctance Motor
作者机构：Sri Sivasubramaniya Nadar College of EngineeringKalavakkamTamilnadu603110India
出 版 物：《Intelligent Automation & Soft Computing》 (智能自动化与软计算（英文）)
年 卷 期：2023年第35卷第1期
页 面：997-1014页
核心收录：
学科分类：08[工学] 0812[工学-计算机科学与技术（可授工学、理学学位）]
主 题：Bridgeless hybrid resonant converter switched reluctance motor BR converter hysteresis current controller PI controller WOA
摘 要：The Power Factor Correction(PFC)in Switched Reluctance(SR)motor is discussed in this *** SR motors are applicable for multiple applications like electric vehicles,wind mills,machineries *** doubly salient structure of SR motor causes the occurrence of torque ripples,which affects the power factor of the *** improve the power quality,the power factor has to be corrected and the ripples have to be *** order to achieve these objectives,a novel power factor correction(PFC)method is proposed in this ***,the conventional Diode Bridge Rectifier(DBR)is replaced by a Bridgeless Hybrid Resonant(HR)converter,which assists in improvising the output in a wider *** converter is chosen because of having variety of beneficial measures including high *** converter’s output is fed to the SR motor by means of an asymmetric Bridge Resonant(BR)*** proposed converter operates in continuous mode of conduction with the switching frequency of 10 KHz.A hysteresis current controller and Proportional Integral(PI)controller are utilized for reducing the harmonics in the source current along with the regulation of output *** addition,the speed control of SR motor is accomplished by means of the Whale Optimization Algorithm(WOA)assisted PI *** proposed methodology is effective for the control of unity power factor,torque and current *** Total Harmonic Distortion(THD)of the source current is also minimized,which suits the standard of International Electrotechnical Comission IEC *** this methodology,the power factor of 0.99 is achieved with 97%efficiency and 3.92%*** proposed methodology is validated in simulation by MATLAB and in hardware by FPGA Spartan 6E.
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