AN EFFICIENT 3-DIMENSIONAL DISCRETE WAVELET TRANSFORM ARCHITECTURE FOR VIDEO PROCESSING APPLICATION

作     者：Ganapathi Hegde Pukhraj Vaya 

作者机构：Department of ECE Amrita Vishwa Vidyapeetham Amrita School of Engineering 

出 版 物：《Journal of Electronics(China)》 (电子科学学刊（英文版）)

年 卷 期：2012年第29卷第6期

页      面：534-540页

学科分类：12[管理学] 1201[管理学-管理科学与工程(可授管理学、工学学位)] 08[工学] 

主　　题：3-D Discrete Wavelet Transform (3-DDWT) Lifting scheme Pipelining Video coding Low power 

摘      要：This paper presents an optimized 3-D Discrete Wavelet Transform (3-DDWT) architecture. 1-DDWT employed for the design of 3-DDWT architecture uses reduced lifting scheme approach. Further the architecture is optimized by applying block enabling technique, scaling, and rounding of the filter coefficients. The proposed architecture uses biorthogonal (9/7) wavelet filter. The architecture is modeled using Verilog HDL, simulated using ModelSim, synthesized using Xilinx ISE and finally implemented on Virtex-5 FPGA. The proposed 3-DDWT architecture has slice register utilization of 5%, operating frequency of 396 MHz and a power consumption of 0.45 W.