Invariant of Enhanced AES Algorithm Implementations Against Power Analysis Attacks
作者机构：Department of Electronic EngineeringDawood University of Engineering&TechnologyKarachiPakistan Faculty of Engineering Sciences and TechnologyHamdard UniversityKarachiPakistan Faculty of Information TechnologySalim Habib UniversityKarachiPakistan Faculty of Computer SciencesSZABISTKarachiPakistan
出 版 物：《Computers, Materials & Continua》 (计算机、材料和连续体（英文）)
年 卷 期：2022年第72卷第7期
页 面：1861-1875页
核心收录：
学科分类：0809[工学-电子科学与技术（可授工学、理学学位）] 08[工学] 0805[工学-材料科学与工程（可授工学、理学学位）] 0812[工学-计算机科学与技术（可授工学、理学学位）]
基 金：Dawood University of Engineering & Technology Karachi Pakistan Hamdard University ORIC Office of Research Innovation & Commercialization
主 题：Side channel attacks power analysis attacks network security masking advance encryption standard
摘 要：The security of Internet of Things(IoT)is a challenging task for researchers due to plethora of IoT *** Channel Attacks(SCA)are one of the major *** prime objective of SCA is to acquire the information by observing the power consumption,electromagnetic(EM)field,timing analysis,and acoustics of the ***,the attackers perform statistical functions to recover the *** Encryption Standard(AES)algorithm has proved to be a good security solution for constrained IoT *** paper implements a simulation model which is used to modify theAES algorithm using logicalmasking *** invariant of the AES algorithm hides the array of bits during substitution byte transformation of *** model is used against SCAand particularly Power Analysis Attacks(PAAs).Simulation model is designed on MATLAB *** will give better solution by hiding power profiles of the IoT devices against *** future,the lightweight AES algorithm with false key mechanisms and power reduction techniques such as wave dynamic differential logic(WDDL)will be used to safeguard IoT devices against side channel attacks by using Arduino and field programmable gate array(FPGA).
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